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   <title>Digital design flow</title>
   <!-- Author: Ludovic Jacomme May 2004 -->
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<h1>The main steps of the digital design flow</h1>
<ul>
	<li>Behavioral specification</li>
	<li>RTL synthesis</li>
	<li>Place and Route</li>
</ul>
<br>

<h1>Overview of the behavioral specification step</h1>
<ul>
	<li>During this step the designer can cut the chip in several functional
	blocks interconnected together
	<br><br><img src=beh-spec-split.gif>
	</li>
	<br>

	<li>Then he has to describe, using a hardware description langage (HDL),
	the behavior of each functional block.<br> Each functional block can be:
	</li>
	<ul>
		<li>a Finite State Machine
		<br><img src=beh-spec-fsm.gif>
		</li>
		<li>a set of registers and transfert functions
		<br><img src=beh-spec-rtl.gif>
		</li>
		<li>a set of interconnected other functional blocks
		<br><img src=beh-spec-struct.gif>
		</li>
	</ul>
	<br>

	<li>The behavioral description has to be validate. The designer can use 
	different methods such as:
	<ul>
		<li>digital simulation using a set of stimuli.
		(each stimuli describes the value of inputs pins 
		and the expected values of outputs pins)</li>
		<li>model checking using a set of CTL formulae. (each CTL
		formulae describe a property that the functional block has
		to verified)</li>
	</ul>
</ul>

<h1>The behavioral specification using the Alliance CAD system</h1>


<ul>
	<li>Digital simulation using a set of stimuli:

        <a id="asimut" name="asimut"></a>
        <a id="xpat" name="xpat"></a>
        <a id="genpat" name="genpat"></a>

	<br><img src=beh-spec-asimut.gif><br>

	<ul>
	      <li><a href="tools.html#genpat">GENPAT</a> is used to write
	      digital stimuli. It provides a C
	      interface of a set of functions useful to create stimuli.  It
	      loads a C file describing patterns and run the C compiler.
	      Finally it generates a stimuli file
	      (<a href="tools.html#pat">PAT</a> file format).
	      Note that patterns file can also
	      be written using a simple text editor.
	      <br></li>

	      <li><a href="tools.html#asimut">ASIMUT</a> is a VHDL simulator.
	      It loads behavioral or structural
	      descriptions written according to the Alliance VHDL subsets.
	      <a href="tools.html#asimut">ASIMUT</a> may also be linked with C
	      descriptions of behavioral
	      components. 
	      It loads a stimuli file (<a href="tools.html#pat">PAT</a> file format) and then
	      run the simulation.  The result is dumped in a new pattern file
	      and it can be displayed using <a href="tools.html#xpat">XPAT</a>.

	      <br></li>

	      <li><a href="tools.html#xpat">XPAT</a> is a graphical pattern
	      viewer. It loads a pattern file
	      (<a href="tools.html#pat">PAT</a> file format) 
	      and displays waveforms on a graphical window.
	      <br></li>

        </ul>
        </li>

	<br><li>Digital simulation of FSM descriptions:

        <a id="syf" name="syf"></a>

	<br><br><img src=beh-spec-syf.gif><br><br>

	<ul>
	       <li><a href="tools.html#syf">SYF</a> loads the graph of a Finite
	       State Machine.  This FSM is
	       described in VHDL using predefined templates. It encodes each
	       states of the FSM and tries to minimize the resulting
	       combinatorial logic.
	       Finally it drives a new description using the Alliance VHDL
	       dataflow subset (<a href="tools.html#vbe">VBE</a> file format).
	       <br></li>
       </ul>
       </li>

       <br><li>Digital simulation of VHDL descriptions using Synospys VHDL subset:

       <a id="vasy" name="vasy"></a>

       <br><br><img src=beh-spec-vasy.gif><br><br>

	<ul>
	       <li><a href="tools.html#vasy">VASY</a> can be seen as a VHDL
	       translator.  It loads VHDL
	       behavioral or structural descriptions (written according to the
	       Synopsys <a href="tools.html#vhd">VHDL</a> subset).
	       It then drives one or more VHDL descriptions using the Alliance
	       VHDL dataflow or structural
	       subsets.  <br> Those Alliance VHDL subsets are small and very
	       particular.  
	       They are called <a href="tools.html#vbe">VBE</a> (VHDL
	       BEhavioral) and <a href="tools.html#vst">VST</a> (VHDL
	       STructural) file format.
	       <br></li>
	</ul>
	</li>

	<br><li>Model checking of behavioral descriptions:

        <a id="mocha" name="mocha"></a>

	<br><br><img src=beh-spec-mocha.gif><br><br>

	<ul>
		<li><a href="tools.html#mocha">MOCHA</a> loads the graph of a
		Finite State Machine
		description.  This FSM is described in VHDL using predefined
		templates.  Then it loads a list of CTL formulae (described in
		CTL file format) and check formally if the given FSM verify CTL
		properties. <a href="tools.html#mocha">MOCHA</a> can also be
		used on a behavioral description
		using the Alliance VHDL dataflow subset (<a href="tools.html#vbe">VBE</a>).
	       <br></li>
       </ul>
       </li>



	<br><li><b>Summary of digital behavioral specification step</b></li>


	<br><br><img src=beh-spec-alliance.gif>
</ul>

<!-- 
-->

<h1>Overview of the RTL synthesis step</h1>
<ul>

	<li>This step consist on a transformation of a behavioral description
	to an optimized netlist of gates (standard cells, macros-cells, datapaths etc ...).
	</li>
	<br>

	<li>The designer can give optimization parameters and constraints to
	be satisfied such as:
	</li>
	<ul>
		<li>delay, arrival/required time
		</li>
		<li>surface
		</li>
		<li>power consumption
		</li>
		<li>etc ...
		</li>
	</ul>
	<br>

	<li>The RTL synthesis step has to be validate. The designer can use 
	different methods such as:
	<ul>
		<li>Post synthesis digital simulation 
		</li>
		<li>Formal proof
		</li>
	</ul>
</ul>

<!--
-->

<h1>The RTL synthesis step using the Alliance CAD system</h1>

<ul>
	<li>Logic synthesis and standard cell mapping

        <a id="boom" name="boom"></a>
        <a id="boog" name="boog"></a>
        <a id="loon" name="loon"></a>
	<a id="proof" name="proof"></a>

	<br><br><img src=rtl-synth-logic.gif><br><br>

	<ul>
		<li><a href="tools.html#boom">BOOM</a> is used for the first
		step of the synthesis process.
		It loads a behavioural description 
		(<a href="tools.html#vbe">VBE</a>), if possible a parameter
		file, and it builds an equivalent boolean network.
		From one hand it minimizes the boolean expression
		of each nodes of the network, and on the other hand it factorizes 
		equivalent nodes. The result is an equivalent boolean network where
		the maximum depth is smaller and where boolean nodes have been factorized.
	        <br></li>

		<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
	        <br></li>
		
		<li><a href="tools.html#proof">PROOF</a> is an equivalence
		checker. It loads two behavioural descriptions
		(<a href="tools.html#vbe">VBE</a>) and check their equivalence using formal technics.
	        <br></li>

		<li><a href="tools.html#boog">BOOG</a> is used for the second
		step of the synthesis process.
		It loads a behavioural description 
		(<a href="tools.html#vbe">VBE</a>) beforehand optimized
		with <a href="tools.html#boom">BOOM</a> 
		and builds an equivalent boolean network. It loads also a library of standard
		cells and in option a parameter file.
		For each boolean function of each node of the network,
		it tries to find in the given library, a cell or a set of cells that produce
		the same boolean function. This step is often called standard cell mapping.
		The result is a netlist of cells with an equivalent behavior.
	        <br></li>

		<li><a href="tools.html#loon">LOON</a> is used for the last
		step of the synthesis process.
		It loads a netlist of gates described in VHDL (<a href="tools.html#vst">VST</a>).
		It loads also a library of standard cells and in option a parameter file.
		<a href="tools.html#loon">LOON</a> computes the critical path
		and performs a gate repowering to
		decrease its delay and global capacitance.
		The result is an optimized netlist described in VHDL 
		(<a href="tools.html#vst">VST</a>).
	        <br></li>

        </ul>
        </li>
	<br>

	<li>Handmake synthesis

        <a id="genlib" name="genlib"></a>
        <a id="xsch" name="xsch"></a>

	<br><br><img src=rtl-synth-genlib.gif><br><br>

	<ul>
		<li><a href="tools.html#genlib">GENLIB</a> provides a C
		interface of a set of functions useful to create 
		a netlist of cells or a physical layout. For example given a cell library,
		a simple C function call is enough to create an instance of a cell.
		The result is a netlist (or a physical layout) built during the sequential
		execution of the C source code.
	        <br></li>

		<li><a href="tools.html#xsch">XSCH</a> is the graphical
		schematic viewer of Alliance. It loads a netlist
	       	(<a href="tools.html#vst">VST</a> file
		format) and displays it on a graphical window.
		<br></li>

		<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
	        <br></li>
        </ul>
        </li>
	<br>

	<li>Data-path synthesis
	<br><br><img src=rtl-synth-dp.gif><br><br>

	<ul>
		<li><a href="tools.html#genlib">GENLIB</a> provides also a C
		interface for several macro-cells generators such
		as rom generator/register file generator etc ... 
		The layout and the netlist of a complex data-path can be easily 
		generated with only simple calls to predefined C functions.
	        <br></li>

		<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
	        <br></li>
        </ul>
        </li>
	<br>

	<li>FSM synthesis and state graph minimisation:

        <a id="fmi" name="fmi"></a>
        <a id="fsp" name="fsp"></a>

	<br><br><img src=rtl-synth-fmi.gif><br><br>

	<ul>
	       <li><a href="tools.html#fmi">FMI</a> loads the graph of a Finite
	       State Machine (<a href="tools.html#fsm">FSM</a> file format).
	       In the given FSM,  <a href="tools.html#fmi">FMI</a> finds all
	       equivalent states and merges them all
	       together. The result is a new FSM, that still equivalent, but with a
	       reduced number of states.
	       Finally it drives this new description using <a href="tools.html#fsm">FSM</a>
	       file format.
	       <br></li>

	      <li><a href="tools.html#fsp">FSP</a> is an FSM equivalence
	      checker. It loads the graph of two FSMs and checks formally
	      (using a FSM product based algorithm) if they have exactly the
	      same behavior.
	      <br></li>

	      <li><a href="tools.html#syf">SYF</a> is a Finite State Machine synthesizer.
	      <br></li>

	      <li><a href="tools.html#b2f">B2F</a> is a Finite State Machine
	      abstractor.
	      It loads a RTL VHDL description (<a href="tools.html#vbe">VBE</a> file format).
	      It then build the graph of an equivalent Finite State Machine, using a symbolic
	      simulation algorithm.  This tool does the inverse operation of the FSM synthesizer 
	      <a href="tools.html#syf">SYF</a>
	      <br></li>
        </ul>
        </li>

</ul>

<!-- 
-->

<h1>Overview of the Place & Route step</h1>
<ul>

	<li>This step consist on a transformation of a netlist description
	to a physical layout.
	</li>
	<br>

	<li>The designer can give some parameters and constraints to
	be satisfied such as:
	</li>
	<ul>
		<li>an initial placement of the cells
		</li>
		<li>a position for each physical connectors 
		</li>
		<li>a form factor
		</li>
		<li>number of metal layers to be used
		</li>
		<li>etc ...
		</li>
	</ul>
	<br>

	<li>The place and route step has to be validated. The designer has to use 
	different methods such as:
	<ul>
		<li>Netlist exctration and netlist comparison
		</li>
		<li>Design rule checking
		</li>
		<li>Functionnal abstraction
		</li>
	</ul>
</ul>

<!--
-->

<h1>The place and route step using the Alliance CAD system</h1>

<ul>
	<li>Overcell place and route

        <a id="ocp" name="ocp"></a>
        <a id="nero" name="nero"></a>

	<br><br><img src=place-route-ocpr.gif><br><br>

	<ul>
		<li><a href="tools.html#ocp">OCP</a> is a placement tool. It
		loads a netlist of standard cells.
		The designer can specifies eventually connectors placement by given
		a parameter file (IOC file format). 
		If there are non standard cell blocks in the netlist, the designer
		has to give a placement for those blocks.
		<a href="tools.html#ocp">OCP</a> then uses a simulated
		annealing algorithm to find a placement
		of all the netlist's cells, that minimized the length of nets.
		The result is a physical symbolic layout file with physical connectors
		and placed cells (<a href="tools.html#ap">AP</a> file format).
	        <br></li>

		<li><a href="tools.html#nero">NERO</a>(previously OCR) is the overcell
                router of Alliance. It loads a netlist and a 
		physical placement file. The designer can give other parameters such
		as the number of metal layer he would like to use.
		The result is a physical symbolic layout view where each net 
		of the netlist has been routed (<a href="tools.html#ap">AP</a> file format).
		<br></li>

        </ul>
        </li>
	<br>


	<li>Pad ring place and route
        <a id="ring" name="ring"></a>

	<br><br><img src=place-route-ring.gif><br><br>

	<ul>
		<li><a href="tools.html#ring">RING</a> loads a netlist of pads
		interconnected with a "core" block.
		The designer can give a relative placement for those pads (RIN file format).
		After loading the physical view of the pads and the core, <a
			href="tools.html#ring">RING</a> 
		place and route them all together, with a special treatment for
		the power supply nets.
		The result is a physical symbolic layout 
		(<a href="tools.html#ap">AP</a> file format).
	        <br></li>
        </ul>
        </li>
	<br>

	<li>Place and route validation

        <a id="lynx" name="lynx"></a>
        <a id="cougar" name="cougar"></a>
        <a id="lvx" name="lvx"></a>
        <a id="druc" name="druc"></a>
        <a id="graal" name="graal"></a>

	<br><br><img src=place-route-valid.gif><br><br>

	<ul>
		<li><a href="tools.html#cougar">LYNX</a> (called now COUGAR) is a
		hierarchical netlist extractor.
		It loads a symbolic or real physical view and given a technological
		file (RDS file format) it extracts a netlist 
		(<a href="tools.html#al">AL</a> file format).
	        <br></li>

		<li><a href="tools.html#lvx">LVX</a> is simple a netlist comparator.
	        <br></li>

		<li><a href="tools.html#druc">DRUC</a> is a hierarchical design rule checker.
		It loads a symbolic physical view and given a technological
		file (RDS file format) it verifies design rules.
	        <br></li>

		<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
	        <br></li>

		<li><a href="tools.html#graal">GRAAL</a> is a hierarchical symbolic layout editor.
	        <br></li>

        </ul>
        </li>
	<br>

	<li>Symbolic layout to real layout

        <a id="s2r" name="s2r"></a>
        <a id="dreal" name="dreal"></a>

	<br><br><img src=place-route-s2r.gif><br><br>

	<ul>
		<li>Given a technological file, <a href="tools.html#s2r">S2R</a> transforms 
		a symbolic layout (lambda) to a real equivalent layout (micron).
	        <br></li>

		<li><a href="tools.html#dreal">DREAL</a> is the real layout editor of Alliance.
	        <br></li>

		<li><a href="tools.html#cougar">LYNX</a> is the netlist extractor of Alliance.
	        <br></li>
        </ul>
        </li>
	<br>
</ul>


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